<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>Cache on Flip The Bit</title><link>https://flipthebit.dev/tags/cache/</link><description>Recent content in Cache on Flip The Bit</description><generator>Hugo</generator><language>en-us</language><copyright>fpgahero.com (CC BY-SA 4.0)</copyright><lastBuildDate>Tue, 26 Nov 2024 00:00:00 +0000</lastBuildDate><atom:link href="https://flipthebit.dev/tags/cache/index.xml" rel="self" type="application/rss+xml"/><item><title>Cache me if you can #1: An intro to what caches are and why you need one</title><link>https://flipthebit.dev/blog/cache-me-if-you-can-1/</link><pubDate>Tue, 26 Nov 2024 00:00:00 +0000</pubDate><guid>https://flipthebit.dev/blog/cache-me-if-you-can-1/</guid><description>&lt;p&gt;My theoretical computer science professor once remarked, “What do IT professionals say when
there&amp;rsquo;s a performance issue? Let’s add another cache! &amp;#x1f604;” When dealing with memory systems,
it’s common to encounter saturation of throughput or pipeline stalls caused by unpredictable
and high read/write latency. Implementing caches can effectively eliminate this bottleneck in most cases.&lt;/p&gt;
&lt;p&gt;Unfortunately, the performance of a system is limited by its weakest component. In modern computing,
processors have scaled remarkably well, with their performance increasing by approximately 100 times
since 1999. However, this improvement does not extend to memory systems. Since 1999:&lt;/p&gt;</description></item></channel></rss>